1. Technical Field
Embodiments of the invention relate generally to Delay Locked Loops (DLLs) and more particularly to multiple phase delay locked loops with equal-spaced phase outputs.
2. Prior Art
Multiple phase DLLs are used in a wide variety of electronic applications such as clock and data recovery, frequency synthesis, and generation of clock pulses for sampling in high speed Analog-to-Digital Converters (ADCs). For optimal use in such a wide variety of applications, it is desirable for the DLL to have a broad frequency range of operation. However, the frequency range over which the DLL can be operated, is limited by a delay range that is supported by a delay line of the DLL.
Some of the existing multiphase DLLs that work over a wide frequency range of operation use a dual loop design. In the dual loop design, a coarse control loop can significantly change the delay line's delay and a fine control loop with a small delay range then produces the required delay. However, the coarse control loop is implemented by digitally switching delay elements of the delay line, which considerably increases the power consumption of the DLL. Further, such implementations involve significant increase in die area.
Another existing technique for generating multiple phases uses a small number of delay elements or cells to generate a few phases. The other required phases are obtained by interpolating between these phases. However, the use of interpolation techniques for generating multiple phases result in low slew rates of clock outputs of the delay cells. So the DLL clock outputs are susceptible to noise and jitter.